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This X24C08 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. 8K
ICmic
IC MICROSYSTEMS
TM
X24C08
Serial E PROM
2
1024 x 8 Bit
TYPICAL FEATURES
DESCRIPTION
The X24C08 is a CMOS 8,192 bit serial E PROM, internally organized 1024 x 8. The X24C08 features a serial interface and software protocol allowing operation on a simple two wire bus. The X24C08 is fabricated with Xicor's advanced CMOS Textured Poly Floating Gate Technology. The X24C08 utilizes Xicor's proprietary Direct WriteTM cell providing a minimum endurance of 100,000 cycles
2
*2.7V to 5.5V Power Supply *Low Power CMOS
--Active Read Current Less Than 1 mA --Active Write Current Less Than 3 mA
*Internally Organized 1024 x 8 *2 Wire Serial Interface
--Standby Current Less Than 50 A
--Bidirectional Data Transfer Protocol *Sixteen Byte Page Write Mode --Minimizes Total Write Time Per Byte *Self Timed Write Cycle --Typical Write Cycle Time of 5 ms *High Reliability
--Endurance: 100,000 Cycles --Data Retention: 100 Years
and a minimum data retention of 100 years.
*8 Pin Mini-DlP, 8 Pin SOIC and 14 Pin
SOIC Packages
FUNCTIONAL DIAGRAM
(8) V CC (4) V SS
(7) TEST
START CYCLE
START STOP
H.V. GENERATION TIMING
& CONTROL (5) SDA LOGIC
CONTROL LOGIC
SLAVE ADDRESS REGISTER
(6) SCL (3) A2 (2) A1 (1) A0
+COMPARATOR
LOAD
INC
XDEC
E PROM 64 X 128
2
WORD ADDRESS COUNTER
R/W
YDEC 8 CK PIN DATA REGISTER
D OUT
D
OUT ACK
3842 FHD F01
(c) Xicor, 1991 Patents Pending
3842-1
1
Characteristics subject to change without notice
X24C08
PIN DESCRIPTIONS
Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull-Up
PIN CONFIGURATION
SOIC
NC
A 0 A 1
1 2 3 4 5 6 7
14 13 12 X24C08 11 10 9 8
NC
V CC TEST NC
NC
A 2 V SS
SCL SDA NC
3842 FHD F03
NC
Resistor selection graph at the end of this data sheet.
Address (A0, A1) A0 and A1 are unused by the X24C08; however, they must be tied to VSS to insure proper device operation. Address (A2) The A2 input is used to set the appropriate bit of the seven bit slave address. This input can be used static or actively driven. If used statically, it must be tied to VSS or VCC as appropriate. If actively driven, it must be driven
DIP/SOIC 1 2 3 4 X24C08 8 7 6 5
A 0 A 1 A 2 V SS
V
CC TEST SCL
SDA
3842 FHD F02
to VSS or to VCC. PIN NAMES Symbol A0-A2 SDA SCL TEST VSS VCC NC Description Address Inputs Serial Data Serial Clock Hold at VSS Ground Supply Voltage No Connect
3842 PGM T01
2
X24C08
DEVICE OPERATION
The X24C08 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24C08 will be considered a slave in all
Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The X24C08 continuously monitors the SDA and SCL lines for the start condition and will not respond to any
command until this condition has been met.
Stop Condition All communications must be terminated by a stop condition which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the X24C08 to place the device into the standby power mode after a read sequence. A stop condition can only be issued after the transmitting device has released the
applications.
Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
bus.
Figure 1. Data Validity
SCL
SDA DATA STABLE DATA CHANGE
3842 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3842 FHD F07
3
X24C08
lected, the X24C08 will respond with an acknowledge after the receipt of each subsequent eight bit word.
In the read mode the X24C08 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the X24C08 will continue to transmit data. If an acknowledge is not detected, the X24C08 will terminate further data transmissions. The master must then issue a stop condition to return the X24C08 to the standby power mode and
Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data. Refer to Figure 3.
The X24C08 will respond with an acknowledge after recognition of a start condition and its slave address. If
both the device and a write operation have been se-
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
3842 FHD F08
4
X24C08
DEVICE ADDRESSING
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see Figure 4). For the X24C08 this is fixed as The last bit of the slave address defines the operation to be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24C08 monitors the SDA bus comparing the slave address being transmitted with its slave address (device type and state of A2 input.) Upon a correct compare the X24C08 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24C08 will execute a read or write
1010[B]. Figure 4. Slave Address
DEVICE TYPE IDENTIFIER 1 0 1 0 HIGH ORDER WORD ADDRESS
operation. WRITE OPERATIONS
A2
A1
A0
R/W
DEVICE ADDRESS
Byte Write For a write operation, the X24C08 requires a second address field. This address field is the word address,
comprised of eight bits, providing access to any one of 1024 words in the array. Upon receipt of the word address the X24C08 responds with an acknowledge, and awaits the next eight bits of data, again responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the X24C08 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the X24C08 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
3842 FHD F09
The next bit addresses a particular device. A system could have up to two X24C08 devices on the bus (see
Figure 10). The two addresses are defined by the state of the A2 input. The next two bits of the slave address field are an extension of the array's address and are concatenated with the eight bits of address in the word address field, providing direct access to the whole 1024 x 8 array.
Figure 5. Byte Write
S T BUS ACTIVITY: MASTER
A R
SLAVE ADDRESS
WORD ADDRESS
DATA
S T
O P
T S
A C A C A C
SDA LINE
BUS ACTIVITY: X24C08
P
K
K
K
3842 FHD F10
5
X24C08
Flow 1. ACK Polling Sequence
WRITE OPERATION COMPLETED
Page Write The X24C08 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation, but instead of terminating the write cycle after the first data word is transferred, the master can
ENTER ACK POLLING
transmit up to fifteen more words. After the receipt of each word, the X24C08 will respond with an acknowl-
edge.
After the receipt of each word, the four low order address bits are internally incremented by one. The high order six bits of the word address remain constant. If the master should transmit more than sixteen words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence. Acknowledge Polling The disabling of the inputs can be used to take advan- tage of the typical 5 ms write cycle time. Once the stop condition is issued to indicate the end of the host's write operation the X24C08 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the X24C08 is still busy with the write operation no ACK will be returned. If the X24C08 has completed the write operation an ACK will be returned and the host can then proceed with the next
ISSUE START
ISSUE SLAVE ADDRESS AND R/W = 0
ISSUE STOP
ACK RETURNED?
NO
YES
NEXT OPERATION
NO
A WRITE? YES ISSUE STOP
ISSUE BYTE ADDRESS
PROCEED
read or write operation. Refer to Flow 1.
PROCEED
3842 FHD F11
Figure 6. Page Write
S T BUS ACTIVITY: MASTER
A R T S
SLAVE ADDRESS
WORD ADDRESS n
DATA n
DATA n+1
DATA n+15
S T
O P
SDA LINE
BUS ACTIVITY: X24C08
P A C K A C K A C K A C K A C K
3842 FHD F12
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
6
X24C08
READ OPERATIONS
Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read and The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 7 for the sequence of address, acknowledge and data transfer. Random Read Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, and the slave address followed by the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the X24C08 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. Refer to Figure 8 for the address, acknowledge and data transfer sequence.
sequential read.
It should be noted that the ninth clock cycle of the read operation is not a "don't care." To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Current Address Read Internally the X24C08 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the X24C08
issues an acknowledge and transmits the eight bit word.
Figure 7. Current Address Read
S T BUS ACTIVITY: MASTER
A R T S
SLAVE ADDRESS
S T
O P
SDA LINE
BUS ACTIVITY: X24C08
P A C K
DATA
3842 FHD F13
Figure 8. Random Read
S T BUS ACTIVITY: MASTER S T
A R T S
SLAVE ADDRESS
WORD ADDRESS n
A R T S
SLAVE ADDRESS
S T
O P
SDA LINE
BUS ACTIVITY: X24C08
P A C K
A C K
A C K
DATA n
3842 FHD F14
7
X24C08
The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read operations increments all address bits, allowing the entire memory contents to be serially read during one operation. At the end of the address space (address 1023) the counter "rolls over" to address 0 and the X24C08 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowl-
Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted as with the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The X24C08 continues to out- put data for each acknowledge received. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition.
edge and data transfer sequence.
Figure 9. Sequential Read
SLAVE ADDRESS A C K A C K A C K
S T
O P
BUS ACTIVITY: MASTER
SDA LINE
BUS ACTIVITY: X24C08
P A C K
DATA n
DATA n+1
DATA n+2
DATA n+x
3842 FHD F15
Figure 10. Typical System Configuration
V
CC
PULL-UP RESISTORS SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER
3842 FHD F16
8
X24C08
ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. -65C to +135C *COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi-
Storage Temperature ...................... -65C to +150C Voltage on any Pin with Respect to VSS ................................. -1.0V to +7V D.C. Output Current ........................................... 5 mA Lead Temperature (Soldering, 10 Seconds) .............................. 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0C -40C -55C Max. 70C +85C +125C
tions for extended periods may affect device reliability.
Supply Voltage X24C08 X24C08-3.5 X24C08-3 X24C08-2.7
Limits 4.5V to 5.5V 3.5V to 5.5V 3V to 5.5V 2.7V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over recommneded operating conditions, unless otherwise specified.)
Limits Symbol lCC1 lCC2 ISB1(1) ISB2(1) ILI ILO VlL(2) VIH(2) VOL Parameter VCC Supply Current (Read) VCC Supply Current (Write) VCC Standby Current VCC Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Min. Max. 1 3 150 50 10 10 VCC x 0.3 -1.0 VCC x 0.7VCC + 0.5 0.4 mA A A A A V V V Units Test Conditions
SCL = VCC x 0.1/VCC x 0.9 Levels @ 100 KHz, SDA = Open,
All Other Inputs = GND or VCC - 0.3V
SCL = SDA = VCC - 0.3V, All Other Inputs = GND or VCC, VCC = 5.5V SCL = SDA = VCC - 0.3V, All Other Inputs = GND or VCC, VCC = 3V
VIN = GND to VCC VOUT = GND to VCC
IOL = 3 mA
3842 PGM T02
CAPACITANCE TA = 25C, F = 1.0MHZ, VCC = 5V
Symbol CI/O(3) CIN(3)
Test Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Max. 8 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
3842 PGM T04
Notes:(1)Must perform a stop command prior to measurement. (2)VIL min and VIH max. are for reference only and are not 100% tested. (3)This parameter is periodically sampled and not 100% tested.
9
X24C08
A.C. CONDITIONS OF TEST Input Pulse Levels
Input Rise and Fall Times
EQUIVALENT A.C. LOAD CIRCUIT
5.0V 1533 Output
3842 PGM T05
VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5
I/O Timing Levels
100pF
3842 FHD F18
A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits
Symbol tSCL tI tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH
Parameter SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs SCL Low to SDA Data Out Valid Time the Bus Must Be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Parameter Power-Up to Read Operation Power-Up to Write Operation Max. 1 5
Min. 0 0.3 4.7 4.0 4.7 4.0 4.7 0 250
Max. 100 100 3.5
Units KHz ns s s s s s s s
1 300 4.7 300 Units ms ms
ns s ns s ns
3842 PGM T06
POWER-UP TIMING Symbol
t tPUW(4)
(4) PUR
Bus Timing
t
3842 PGM T07
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
SDA IN
t t t
AA
DH
BUF
SDA OUT
3842 FHD F04
Note:
(4)t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
10
X24C08
WRITE CYCLE LIMITS Symbol t
(6) WR
Parameter Write Cycle Time
Min.
Typ. 5
(5)
Max. 10
Units ms
3842 PGM T08
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal
bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24C08
address.
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK
t WR
STOP CONDITION
START CONDITION
X24C08 ADDRESS
3842 FHD F05
Notes:(5) Typical values are for T A = 25C and nominal supply voltage (5V). (6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the device
requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM INPUTS
Must be steady May change from Low to
OUTPUTS
Will be steady Will change from Low to
120 RESISTANCE (K) 100 80 60 40 20 0 0 20 40
R MIN
V
=
CC MAX I OL MIN
=1.8K
R MAX
=
t MAX R C BUS
MAX. RESISTANCE
High
May change from High to
High
Will change from High to
Low
MIN. RESISTANCE
Low
Changing: State Not
Don't Care: Changes
60
80100120
Allowed N/A
3842 FHD F17
Known
Center Line is High
BUS CAPACITANCE (pF)
Impedance
11
X24C08
NOTES
12
X24C08
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00)
0.228 (5.80) 0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0 - 8
0.0075 (0.19) 0.010 (0.25)
0.027 (0.683) 0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)
3926 FHD F22
13
X24C08
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.092 (2.34) DIA. NOM.
0.255 (6.47) 0.245 (6.22) PIN 1 INDEX
PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE
0.140 (3.56) 0.130 (3.30)
0.150 (3.81) 0.125 (3.18)
0.020 (0.51) 0.015 (0.38) 0.062 (1.57) 0.058 (1.47)
0.110 (2.79) 0.090 (2.29)
0.020 (0.51) 0.016 (0.41)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP. 0.010 (0.25)
0 15
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F01
14
X24C08
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00)
0.228 (5.80) 0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35) 0.019 (0.49)
0.336 (8.55) 0.345 (8.75)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) X 45 0.020 (0.50)
0 - 8
0.0075 (0.19) 0.010 (0.25)
0.027 (0.683) 0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10
15
X24C08
ORDERING INFORMATION
X24C08 Device P T G -V
VCC Limits Blank = 4.5V to 5.5V 3.5 = 3.5V to 5.5V 3 = 3.0V to 5.5V 2.7 = 2.7V to 5.5V G = RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C
M = Military = -55C to +125C
Package P = 8-Lead Plastic DIP S8 = 8-Lead SOIC
Part Mark Convention X24C08 XG
S14 = 14-Lead SOIC
P = 8-Lead Plastic DIP S8 = 8-Lead SOIC
S = 14-Lead SOIC X
G = RoHS compliant lead free
Blank = 4.5V to 5.5V, 0C to +70C I = 4.5V to 5.5V, -40C to +85C B = 3.5V to 5.5V, 0C to +70C C = 3.5V to 5.5V, -40C to +85C D = 3.0V to 5.5V, 0C to +70C E = 3.0V to 5.5V, -40C to +85C F = 2.7V to 5.5V, 0C to +70C G = 2.7V to 5.5V, -40C to +85C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.
U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
16

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